rev. 0.2 9/11 copyright ? 2011 by silicon laboratories AN611 AN611 u sing the iso volt dc/dc c onverter r eference d esign 1. design overview the isovolt isolated dc/dc reference design shown in fi gure 1 is a low-cost, robust , isolated dc/dc converter capable of delivering a maximum of 3 w of output power. this isolated power conv erter enables silicon labs isolation products to be powered from a single bias supply, eliminating the need for separate supplies on both sides of the isolation device. this design features fold-back current limiting and thermal shutdown protection, low emi operation, and high (78%) operating efficiency. input vo ltage ranges are 3.3 or 4.5 vdc to 5.5 vdc and generate isolated output voltages of 3.3, 5.0, 7.0, or 24 v, depen ding on the transformer and output regulator used. referring to figure 1, the isovolt reference design is based on push-pull switching topology. the timing generator is a ct600-px0624gm mcu, which has been factory-programmed to generate primary-side transformer switch timing. figure 1. isovolt isolated dc/dc block diagram this mcu has a maximum bias voltage of 3.3 v, allowing applications having 2.7 v < vin < 3.3 v dc. higher values of vin require the addition of input regulator (u2). the ti ming generator outputs are conditioned by high and low- side gate driver circuits, which driv e the switches on transformer t1's primary at a frequency of 500 khz. the resulting ac voltage on the secondary-side is rectified by a full-wave schottky diode circuit and filtered by a bulk capacitor (c10). an active clamp circ uit sinks current during light output loads (50 ma or less) to ensure the dc voltage stays below the maximum input voltage value of t he linear output regulator. the resulting conditioned dc voltage is regulated by a linear output regulator (u4). the isovolt reference design bo ard (see figure 4) also contains digital isolator u3 (silicon labs si864ibc with three forward channels and one reverse channel) for cust omer use. the combination of isovolt and the onboard isolator is useful in applications, such as isolated serial ports. the user c an connect external signals to input blocks j1 and j2, and vout+ supplies bias to the output side of the isolator. note: u3 maximum vdd2 is 5.5 v. if vdd2 exceeds 5 v, the value of resistor r6 must be increased to ensure that u3 pin 16 does not exceed 5.5 v under any operating conditions. for bom, schematic, and layout details, see the discrete iso- volt isolated dc-dc converter re ference design users guide. u1 c8051t600 \ gm vdd gnd 5 3 11 c3 0.1uf ceramic c1 10uf 1 c2 0.1 u2 vss vin vout 2 3 1 ? xc6215p 3,2 vin+ (p1) vin \ (p2) p0.3 c6 ? 470pf ? npo r6 220 vin+ 2 3 1 q4 r3 1.0k c7 ? 470pf ? npo 3 2 1 q5 r1 200k tp12 /rst 8 r4 1.0 tp3 r11 200k 1 2 3 tp5 q6 4 6 c4 ? 470pf ? npo r9 220 vin+ 2 3 1 q1 r2 1.0k c5 ? 470pf ? npo 3 2 1 q2 r7 200k r10 1.0 tp8 r5 200k 1 2 3 q3 p0.4 tp6 tp11 r12 0.0 c8 ? nopop c14 x7r 4.7uf r17 100k j3 3.3v vdd1 gnd1 a1 a2 a3 a4 u3 si8641bb vdd2 gnd2 b1 b2 b3 b4 c13 1uf r13* r14 r15 r16 vin+ vout+ *r12 \ r15 ? = ? 100 2 1 3 4 5 gnd1 6 en/nc 7 8 15 16 14 13 12 11 10 9 gnd2 en/nc2 7vdc ? max c10 10uf u4 c11 x5r 10uf vout+ (p3) vss vin vout d1 d2 t1 xfmr xc6220b 2 5 1 ce 3 8 7,6 5 vout \ (p4) r19 100 r20 10k r18 8.25k d3 q8 j1 j2 r6 0.0 c12 1uf low \ side ? driver high \ side ? driver rectifiers ? and ? active ? clamp output ? regulator digital ? isolator timing ? generator input ? regulator tp14 tp13
AN611 2 rev. 0.2 1.1. gate driver circuits while the timing generator (u1, figur e 1) has a maximum vdd of 3.3 v, many applications will have a vin of 4.5 v to 5.5 v dc; therefore, the gate driver s must provide a 0 to vin output swing from a maximum input signal of 3.3 v. to meet this criterion, the discrete gate driver circuits use a bootstrap circuit to level-shift driver output swing. referring to figure 2, when the mcu ou tput is low, high-side transistor q1 is on, and bootstrap capacitor c4 charges to approximately (vin C 0.7 v). when the mcu outp ut transitions high, q1 base is driven by vboot (i.e. vboot = mcu vout + vin C0.7 v ~ 7.6 v assuming vin = 5. 0 v, mcu vout = 3.3 v, waveform a, figure 2). this high-voltage swing abruptly turns high-side transistor q1 off and low-side transistor q2 on. note the low-side rc circuit (c5, r2) provides speed-up for q2 (channel 2, figure 2). figure 2. bootstrap driver operation the resistor, r3, helps to provide a path for pre-charging the bootstrap capacitor, c4, as well as to provide dc bias for transistor q1. it also helps to keep the base of transistor pulled high t ill the microcontroller starts switching. the value of r3 should be chosen based on minimum turn -on time (or minimum duty-cycle) of the high-side switch so that there is enough time to discharge the capacitor to bring the voltage at the base of transistor, q1, to its normal value before the next switching cycle begins. equation 1. the capacitor, c4, is chosen such that the dynamic current due to change in voltage across it multiplied by the hfe of transistor q1 should be able to charge the gate capacito r of transistor q3 to turn it on within a short time. the base-emitter reverse bias voltage of the transistor, q1, sh ould not exceed vendor specifications. to prevent the base-emitter voltage from exceeding specified maximum limits during transients, use of a diode clamp between base and emitter with the anode of the diode connected to the transistor base and the cathode to the emitter is recommended. any change in system operating frequency must also compensate the values of the rc circuits at the base of the high-side drive transistor and low-si de drive mosfet. failure to do this can cause cross- conduction, which can lower efficiency or destroy the converter. for best results, the layout files included in the isovolt reference design should be used. any circuit modifications should adhere to these layout guidelines: ?? the driver layout should be as tight as possible to minimize inductance. ?? the driver output should be located as close to the s witching transistor and transformer pads as possible to minimize inductive ringing. ?mcu c4 ? 470pf ? npo r3 220 vin+ r2 1.0k c5 ? 470pf ? npo r1 200k r4 1.0 r5 200k gate ? driver ? 1 ch3 ch2 q1 q2 q3 ch1 gate ? driver ? 2 ch4 vin+ ch1: ch4: ch2: ???q2 ? gate ch3: xfmr high side (10x) xfmr low side (10x) q1 base (2x v in ) 5 & ? t onq4 min ?? ?
AN611 rev. 0.2 3 1.2. active clamp the active clamp shown in figure 3 protects the linear ou tput regulator from excessive input voltages when the converter is operating at an output current of 50 ma or less. at these low currents, the voltage at point a increases. the r18, d3, and r20 network provides a thresh old at the base of q8 such that, as the voltage on point a exceeds 6.8 vdc, q8 gradually turns-on, causing current to flow through r19 to ground and limiting the voltage excursion at point a. figure 3. active clamp the minimum voltage at point a must be greater than the sum of zener voltage d3, base-emitter voltage of q8, and the drop across resistor r18 to turn on transistor q8 so that a minimum load current is absorbed by resistor r19 and the transistor q8. for example, the reference design board uses the torex xc6220b as its 5 v output linear regulator (maximum input voltage specification of 6.5 v). the active clamp is used to limit the regulator input voltage to less than 6.5 v under light load conditions. the zener diode has a value of 5.1 v, and resistor r18 is chosen to limit the current through the zener diode once its clamp voltage is exceeded. current is sunk through transistor q8 such that the voltage at the regulator input remains below 6.5 v. re sistor r19 is appropriately selected for power dissipation. r19 100 r20 10k r18 8.25k d3 q8 ? active ? clamp from ? rectifiers ? and ? bulk ? capacitor to ? output? regulator a
AN611 4 rev. 0.2 1.3. system waveforms figure 4. isovolt reference design board figure 4 shows a populated isovolt reference design board showing the test points for waveform generator u1 outputs (tp6, tp12), gate drive to primary switching mosfets (tp8, tp3), primary side switch drain outputs (tp5, tp11), and the input of the linear regulator output (tp13). the corresponding waveforms at 10% and 100% load are shown in the waveforms in figures 5 through 7.
AN611 rev. 0.2 5 figure 5. gate drive to primary switch tp3 and tp8 figure 6. waveform generator outputs tp6 and tp12 figure 7. ac ripple at the cathode of the secondary rectifier ? ? ?
AN611 6 rev. 0.2 2. adjusting conv erter performance the gate driver used in this reference design is a general -purpose driver that can be used to drive any high- and low-side drive with the proper selection of components. th e selection of the bootstrap capacitor and resistor is important (see "1.1. gate driver circuit s" on page 2 for details). increasing the gate drive current requires higher current drive transistors (e.g. q1 and q2 in figure 2). 2.1. changing output voltage the dc-dc converter can be adapted for different output vo ltages by modifying the turns-ratio of the isolation transformer. the secondary re ctifiers (diodes d1 and d2 shown in figure 1 ) should be rated for at least twice the maximum clamped voltage at the input to the linear regulato r. in practice, it is recommended to use at least 50% overhead above this value to accommodate the voltage spikes due to circuit parasitics. the output filter capacitor should also be rated according to the maximum output voltage generated.
AN611 rev. 0.2 7 3. performance data figure 8. efficiency vs. load for 5 v to 5 v figure 9. load regulation for 5 v to 5 v 0 10 20 30 40 50 60 70 80 90 0 200 400 600 800 %efficiency load_current (ma) push-pull efficiency vs load umec transformer 1:1.2 4.97 4.975 4.98 4.985 4.99 4.995 5 5.005 5.01 0 200 400 600 800 output voltage (v) load current (ma) load regulation umec transformer 1:1.2
AN611 8 rev. 0.2 d ocument c hange l ist revision 0.1 to revision 0.2 ?? changed si8441 to si8641 throughout.
AN611 rev. 0.2 9 n otes :
disclaimer silicon laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon laboratories products. characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. silicon laboratories shall have no liability for the consequences of use of the information supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products must not be used within any life support system without the specific written consent of silicon laboratories. a "life support system" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon laboratories products are generally not intended for military applications. silicon laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear , biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc., silicon laboratories, silicon labs, silabs and the silicon labs logo, cmems?, efm, efm32, efr, energy micro, energy micro logo and combinations thereof, "the worlds most energy friendly microcontrollers", ember?, ezlink?, ezmac?, ezradio?, ezradiopro?, dspll?, isomodem ?, precision32?, proslic?, siphy?, usbxpress? and others are trademarks or registered trademarks of silicon laboratories inc. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders. http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa smart. connected. energy-friendly products www.silabs.com/products quality www.silabs.com/quality support and community community.silabs.com
|
